GPU accelerators should be treated more like vector processors … like vectors they are quite sensitive to memory access patterns. When you hit the right pattern, you get some good performance (assuming your code is integer/single precision based). It still has issues in double precision.

I played with the Fixstar’s Cell (GA-180) we are selling in the Pegasus GPU+Cell. It is basically a PC on a card, with 4GB ram, 2x Powercell 8xi (think Roadrunner Cell units). Writing code for it is relatively easy, though I have to learn how to make effective use of the SPUs with the compilers. This is what I find for a slightly modified code:

AMD: 2.3 GHz Shanghai

landman@pegasus-a3g:~/rzftest$ time ./rzf-amd.exe
pi = 3.141592644040497
error in pi = 0.000000009549296
relative error in pi = 0.000000003039635

real 0m0.740s
user 0m0.736s
sys 0m0.004s

Powercell PPU 2.8 GHz

[landman@pxcab rzftest]$ time ./rzf-cell.exe
pi = 3.141592644040497
error in pi = 0.000000009549296
relative error in pi = 0.000000003039635

real 0m2.794s
user 0m2.784s
sys 0m0.007s

SPU on Powercell 8xi:

[landman@pxcab rzftest]$ time ./rzf-spu.exe
pi = 3.141592644040497
error in pi = 0.000000009549296
relative error in pi = 0.000000003039635

real 0m6.087s
user 0m0.001s
sys 0m0.006s

So as far as acceleration goes, there is a learning curve there as well. I think it is likely a general rule of thumb that in the vast majority of cases, acceleration will require some effort to effect. Our experiments with Cuda yielded similar initial results … only after we understood how to approach the architecture were we able to make effective use of it.

In the case of the SPUs, in aggregate, we should be able to approach 100 GFLOP double precision for 8 of them, so roughly on the order of 12 GFLOP/SPU for double precision. Which is not that far off an AMD or Intel processor core. SPUs have very little local memory, and the PPU manages the memory access for it, so this usually winds up being a bottleneck for codes that haven’t been re-architected for it. My experiment above can’t be construed as the speed of a PPU or an SPU, but it can help set expectations that speed increases which are possible are not automatic without a code re-architecture.

And this is true on Cuda, with SSE, with …

Basically its going to take some effort to get it there.

Of course (a) if there was he might not have been at liberty to talk about it and (b) there’s plenty of people for whom GPUs may be good enough (yes, NAMD, I’m looking at you)..